1. Field of the Invention
The present invention relates to an inverter circuit, and more particularly to an inverter circuit supplying polyphase power.
2. Discussion of the Background
FIG. 20 is a circuit diagram showing a configuration of a background-art inverter circuit 1a and connection of the circuit 1a and peripheral devices. Terminals P and N on both ends of a smoothing capacitor 70 are connected to a not-shown electronic power rectifier which can employ a diode bridge and the like and supplied with substantially-direct current power therefrom. The inverter circuit 1a converts the substantially-direct current power into three-phase electric power and supplies this power for a load 71 such as a motor M.
In the inverter circuit 1a, on each “L” side of U-phase, V-phase and W-phase, i.e., on a side connected to the terminal N provided are IGBTs (Insulated Gate Bipolar Transistor: hereinafter, simply referred to as “transistor”) 20F, 21F and 22F each with a protective diode for producing a regenerative current. On each “H” side of the U-phase, the V-phase and the W-phase, i.e., on a side connected to the terminal P provided are IGBTs 23F, 24F and 25F each with the protective diode. Their The gates of the transistors 20F, 21F, 22F, 23F, 24F and 25F are connected to a controller 10a, and specifically their operations are controlled by a driving circuit 12 included in the controller 10a. Supplied with an overcurrent signal by an overcurrent protective circuit 11, the driving circuit 12 controls the operations of the transistors so that no excess current may flow into the transistor in which an overcurrent possibly flows.
The possibility that an overcurrent flows in the transistor inverter can be detected as follows. Emitters of the transistors 20F, 21F and 22F on the “L” side are connected in common to one end of a resistor 30. A voltage drop caused by a current flowing in the resistor 30 is given to one input end of a comparator 13 through a low-pass filter 45 consisting of a resistor 47 and a capacitor 46. The other input end of the comparator 13 is connected to a power supply 14 for supplying a predetermined voltage Vref. An output of the comparator 13 is given to the overcurrent protective circuit 11. Therefore, when a current large enough to cause a voltage drop higher than the voltage Vref flows in the resistor 13, judging that an overcurrent flows in at least one of the transistors 20F, 21F and 22F, the overcurrent protecttive circuit 11 applies the overcurrent signal to the driving circuit 12. For example, the driving circuit 12 receives the overcurrent signal to turn off the transistors 20F, 21F and 22F.
Thus, the technique to detect an overcurrent by a DC bus detection system is disclosed in e.g., Japanese Patent Application Laid Open Gazette No. 7-298481.
FIG. 21 is a circuit diagram showing a configuration of another background-art inverter circuit 1b and connection of the circuit 1b and peripheral devices. As compared with the inverter circuit 1a, the transistors 20F, 21F and 22F on the “L” side are replaced by transistors 20S, 21S and 22S each comprising a current detection terminal as well as the protective diode. The current detection terminals of the transistors 20S, 21S and 22S are connected in common to the terminal N through resistors 30u, 30v and 30w, respectively.
The inverter circuit 1b comprises a controller 10b. The controller 10b has control units 10u, 10v and low 10w corresponding to the respective phases, which control drivings of the transistors 20S, 21S and 22S, respectively. For example, the control unit 10u comprises a comparator 13u, an overcurrent protective circuit 11u and a driving circuit 12u.
One input end of the comparator 13u is connected to a power supply 14u for supplying the voltage Vref, and the other input end receives a voltage drop across the resistor 30u through a filter 45u having the same constitution as the filter 45 connected to the inverter 1a.
The overcurrent protective circuit 11u gives overcurrent information to the driving circuit 12u on the basis of an output from the comparator 13u. For example, when the voltage drop across the resister 30u is higher than the voltage Vref, judging that an ovecurrent flows in the transistors 20S, the driving circuit 12u given the overcurrent information from the overcurrent protective 11u turns off the transistor 20S. Similarly, the other control units 10v and 10w monitor voltage drops across the resistors 30v and 30w through filters 45v and 45w to control operations of the transistors 21S and 22S, respectively.
Thus, the technique to detect an overcurrent by phase-current detection system using transistors having current detection terminals is disclosed in e.g. Japanese Patent Application Laid Open Gazette No. 9-219976.
The background-art technique to detect an overcurrent by the DC bus detection system has a problem that a loss across the resistor 30 becomes larger since a current flowing in a bus connected to the transistors 20F, 21F and 22F causes the voltage drop across the transistor resistor 30. Further, as the resistor 30, it is necessary to adopt a high-power resistor, so it disadvantageously costs high. Moreover, it is not easy to incorporate such a resistor in the inverter circuit 1a and it is necessary to separately provide the resistor outside the inverter circuit 1a.
The background-art technique to detect an overcurrent by the phase-current detection system has a problem that it is impossible to reduce the size of the inverter circuit 1b since the respective current detection terminals of the transistors 20S, 21S and 22S are connected to the controller 10b to increase the number of interconnection lines. Further, in order to transfer the voltage drops across the resistors 30u, 30v and 30w to the control units 10u, 10v and 10w while avoiding an effect of noise, it is necessary to provide the filters 45u, 45v and 45w corresponding to the respective phases.